Charging Method, Terminal Device, and Power Supply Device

ABSTRACT

A charging method includes the follows. A battery of a terminal device is determined to be charged in a charging mode based on that current status of the terminal device satisfies a condition that the battery of the terminal device is operable to be charged in the charging mode. A communication with the terminal device is conducted to determine a charging voltage or a charging current of the charging mode. An output voltage or output current output to the terminal device is adjusted to enter a constant current phase. A communication with the terminal device is conducted during the constant current phase to receive information of a current voltage of the battery. The output current output to the terminal device is adjusted according to the current voltage of the battery in the constant current phase. A related terminal device and power supply device are also provided.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation application of U.S. patentapplication Ser. No. 15/411,248, filed on Jan. 20, 2017, which is acontinuation of International Application No. PCT/CN2016/070203, filedon Jan. 5, 2016, the contents of both of which are hereby incorporatedby reference in their entireties.

TECHNICAL FIELD

Implementations of the present disclosure relates to charging field, andmore particularly to a charging method, a terminal device, and a powersupply device.

BACKGROUND

Terminal devices (e.g., smart phones) become more and more popular withconsumers. However, the power consumption of terminal devices is great,thus terminal devices need to be charged regularly. As the batterycapacity of terminal devices becomes greater and greater,correspondingly, the charging time becomes longer. How to realize quickcharging is a problem that may be needed to be solved.

In order to achieve the purpose of quick charging, the output current ofa power supply device may be directly increased without consideration ofendurance of a terminal device, as such, a phenomenon of the heating andeven burnout of the terminal device may occur, which may reduce thelifespan of the terminal device.

SUMMARY

In the present disclosure, a charging method, a power supply device, anda terminal device are provided.

In a first aspect, a charging method is provided. The method includesthe follows. A battery of a terminal device is determined to be chargedin a charging mode based on that current status of the terminal devicesatisfies a condition that the battery of the terminal device isoperable to be charged in the charging mode by a power supply device. Acommunication is conducted with the power supply device to determine acharging voltage or a charging current of the charging mode. Acommunication is conducted with the power supply device to transmitinformation of a current voltage of the battery to the power supplydevice after the power supply device adjusts an output voltage or outputcurrent of the power supply device according to the charging voltage orthe charging current of the charging mode and enters a constant currentphase, so as to cause the power supply device to adjust the outputcurrent according to the current voltage of the battery.

In a second aspect, a charging method is provided. The method includesthe follows. A battery of a terminal device is determined to be chargedin a charging mode based on that current status of the terminal devicesatisfies a condition that the battery of the terminal device isoperable to be charged in the charging mode. A communication with theterminal device is conducted to determine a charging voltage or acharging current of the charging mode. An output voltage or outputcurrent output to the terminal device is adjusted according to thecharging voltage or the charging current of the charging mode to enter aconstant current phase. A communication with the terminal device isconducted during the constant current phase to receive information of acurrent voltage of the battery. The output current output to theterminal device is adjusted according to the current voltage of thebattery in the constant current phase.

In a third aspect, a power supply device is provided. The power supplydevice includes at least one processor and a computer readable memorycoupled to the at least one processor and storing at least one computerexecutable instruction therein which, when executed by the at least oneprocessor, causes the at least one processor to perform following acts.A battery of a terminal device is determined to be charged in a chargingmode based on that current status of the terminal device satisfies acondition that the battery of the terminal device is operable to becharged in the charging mode. A communication with the terminal deviceis conducted to determine a charging voltage or a charging current ofthe charging mode. An output voltage or output current output to theterminal device is adjusted according to the charging voltage or thecharging current of the charging mode to enter a constant current phase.A communication with the terminal device is conducted during theconstant current phase to receive information of a current voltage ofthe battery. The output current output to the terminal device isadjusted according to the current voltage of the battery in the constantcurrent phase.

BRIEF DESCRIPTION OF THE DRAWINGS

To better illustrate the technical solution of implementations of thepresent disclosure, the following descriptions will briefly illustratethe accompanying drawings described in the implementations. Obviously,the following described accompanying drawings are some implementationsof the present disclosure. Those skilled in the art can obtain otheraccompanying drawings according to the described accompanying drawingswithout creative work.

FIG. 1 is a schematic diagram illustrating a charging process inaccordance with an implementation of the present disclosure.

FIG. 2 is a schematic diagram illustrating that a power supply deviceimplements a data reception and transmission in accordance with animplementation of the present disclosure.

FIG. 3 is a schematic diagram illustrating a communication sequence of apower supply device in accordance with an implementation of the presentdisclosure.

FIG. 4 is a schematic diagram illustrating a communication sequence of apower supply device in accordance with an implementation of the presentdisclosure.

FIG. 5 is a schematic diagram illustrating a charging method inaccordance with an implementation of the present disclosure.

FIG. 6 is a schematic diagram illustrating a terminal device inaccordance with an implementation of the present disclosure.

FIG. 7 is a schematic diagram illustrating a power supply device inaccordance with an implementation of the present disclosure.

DETAILED DESCRIPTION

In combination with the first aspect, in an implementation manner of thefirst aspect, the first instruction further indicates path impedance ofthe terminal device, the path impedance of the terminal device isconfigured for the power supply device to determine whether the USBinterface is in good contact, or whether impedance of a charge circuitbetween the power supply device and the terminal device is abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the first instruction is 101000YYYYY0, Y indicates 1 bit, and thepath impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, themethod further comprises: receiving, by the terminal device, a replyinstruction of the first instruction from the power supply device,wherein the reply instruction of the first instruction indicates thatthe power supply device supports the quick charging mode, or indicatesthat the power supply device agrees to charge the battery in the quickcharging mode.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the reply instruction of the first instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefirst instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect,communicating, by the terminal device, with the power supply device todetermine the charging voltage of the quick charging mode comprises:transmitting, by the terminal device, a second instruction to the powersupply device, wherein the second instruction indicates that the outputvoltage of the power supply device is high, low, or proper; andreceiving, by the terminal device, a reply instruction of the secondinstruction from the power supply device, wherein the reply instructionof the second instruction indicates that the power supply device hasreceived the second instruction.

Optionally, the second instruction can indicate a current voltage of thebattery, so as to cause the power supply device to directly determinethe output voltage according to the current voltage of the battery.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the second instruction is 101001000YY0, Y indicates 1 bit, YY=11indicates that the output voltage of the power supply device is proper,YY=10 indicates that the output voltage of the power supply device ishigh, YY=01 indicates that the output voltage of the power supply deviceis low, and YY=00 indicates that the communication between the terminaldevice and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the reply instruction of the second instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thesecond instruction, and when XX is any value except 01, it indicatesthat the communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect,communicating, by the terminal device, with the power supply device todetermine the charging current of the quick charging mode comprises:transmitting, by the terminal device, a third instruction to the powersupply device, wherein the third instruction indicates a maximumcharging current currently supported by the terminal device; andreceiving, by the terminal device, a reply instruction of the thirdinstruction from the power supply device, wherein the reply instructionof the third instruction indicates that the power supply device hasreceived the third instruction, or the third instruction indicates thatthe terminal device is ready to enter the constant current phase.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the third instruction is 101010YYY000, Y indicates 1 bit, and themaximum charging current currently supported by the terminal deviceequals to 3000+(YYY*250) mA.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the reply instruction of the third instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thethird instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect,communicating, by the terminal device, with the power supply device toconstantly transmit the information of the voltage of the battery to thepower supply device comprises: transmitting, by the terminal device, afourth instruction to the power supply device, wherein the fourthinstruction indicates the voltage of the battery; and receiving, by theterminal device, a reply instruction of the fourth instruction from thepower supply device, wherein the reply instruction of the fourthinstruction indicates that the power supply device has received thefourth instruction.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and thevoltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, the replyinstruction of the fourth instruction further indicates that the USBinterface is in bad contact, or indicates that the impedance of thecharge circuit between the power supply device and the terminal deviceis abnormal, and is ready to exit the quick charging mode, or indicatesthat the quick charging communication process needs to be reactivated.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the reply instruction of the fourth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefourth instruction, XX=11 indicates that the USB interface is in badcontact, or indicates that the impedance of the charge circuit betweenthe power supply device and the terminal device is abnormal, and isready to exit the quick charging mode, or indicates that the quickcharging communication process needs to be reactivated, and when XX isany value except 01 and 11, it indicates that the communication betweenterminal device and the power supply device becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, themethod further comprises: transmitting, by the terminal device, a fifthinstruction to the power supply device, wherein the fifth instructionindicates a maximum voltage of the battery; and receiving, by theterminal device, a reply instruction of the fifth instruction from thepower supply device, wherein the reply instruction of the fifthinstruction indicates that the power supply device has received thefifth instruction.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and themaximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, a formatof the reply instruction of the fifth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefifth instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, themethod further comprises: executing, by the terminal device, at leastone of following operations when the communication between the powersupply device and the terminal device becomes abnormal, wherein thefollowing operations comprise: exiting the quick charging mode, chargingthe battery in the normal charging mode, stopping charging, orreactivating the quick charging communication process.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, aninstruction transmitted from the terminal device to the power supplydevice comprises multiple bits, when the terminal device transmits anyinstruction, the terminal device firstly transmits a most significantbit (MSB) of the multiple bits of the any instruction; or an instructionreceived from the power supply device by the terminal device comprisesmultiple bits, when the terminal device receives an instruction, theterminal device firstly receives a MSB of the multiple bits of theinstruction.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, clocksignals used in the communication between the power supply device andthe terminal device are provided by the power supply device.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, aninstruction transmitted from the power supply device to the terminaldevice comprises multiple bits, during a process of transmitting each ofthe multiple bits, the power supply device firstly transmits each bit,and then transmits a clock interrupt signal; or a reply instructionreceived from the terminal device by the power supply device comprisesmultiple bits, during a process of receiving each of the multiple bits,the power supply device firstly transmits the clock interrupt signal,and then receives each bit after a preset time interval.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, eachinstruction received from the terminal device by the power supply devicecomprises a 12-bit data, the power supply device receives the 12-bitdata from the terminal device via twelve continuous clock periods of theclock signal, level of previous 500 μs of each of the twelve continuousclock periods is high, and level of latter 10 μs of each of the twelvecontinuous clock periods is low; or each instruction transmitted fromthe power supply device to the terminal device comprises a 5-bit data,the power supply device transmits the 5-bit data to the terminal devicevia five continuous clock periods of the clock signal, level of previous10 μs of each of the five continuous clock periods is low, and level oflatter 500 μs of each of the five continuous clock periods is high.

In combination with the first aspect or any of the above implementationmanners, in another implementation manner of the first aspect, during aprocess that the power supply device receives an instruction from theterminal device, a minimum value of high level of the clock signal usedbetween the power supply device and the terminal device equals to VDD ofthe power supply device minus 0.7V; or during the process that the powersupply device receives an instruction from the terminal device, amaximum value of low level of the clock signal used between the powersupply device and the terminal device is 0.8V; or during a process thatthe power supply device transmits an instruction to the terminal device,a minimum value of high level of the clock signal used between the powersupply device and the terminal device equals to 0.25VDD+0.8V; or duringthe process that the power supply device transmits an instruction to theterminal device, a maximum value of the high level of the clock signalused between the power supply device and the terminal device is 4.5V; orduring the process that the power supply device transmits an instructionto the terminal device, a maximum value of low level of the clock signalused between the power supply device and the terminal device is 0.15VDD.The VDD is a work voltage of the power supply device, and/or the VDD isgreater than 3.2V and less than 4.5V.

In combination with the second aspect, in an implementation manner ofthe second aspect, the first instruction further indicates pathimpedance of the terminal device, the path impedance of the terminaldevice is configured for the power supply device to determine whetherthe USB interface is in good contact, or to determine whether impedanceof a charge circuit between the power supply device and the terminaldevice is abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the first instruction is 101000YYYYY0, Y indicates 1 bit, and thepath impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, themethod further comprises: transmitting, by the power supply device, areply instruction of the first instruction to the terminal device,wherein the reply instruction of the first instruction indicates thatthe power supply device supports the quick charging mode, or indicatesthat the power supply device agrees to charge the battery in the quickcharging mode.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the reply instruction of the first instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefirst instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect,communicating, by the power supply device, with the terminal device todetermine the charging voltage of the quick charging mode comprises:receiving, by the power supply device, a second instruction from theterminal device, wherein the second instruction indicates that theoutput voltage of the power supply device is high, low, or proper; andtransmitting, by the power supply device, a reply instruction of thesecond instruction to the terminal device, wherein the reply instructionof the second instruction indicates that the power supply device hasreceived the second instruction.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the second instruction is 101001000YY0, Y indicates 1 bit, YY=11indicates that the output voltage of the power supply device is proper,YY=10 indicates that the output voltage of the power supply device ishigh, YY=01 indicates that the output voltage of the power supply deviceis low, and YY=00 indicates that the communication between the terminaldevice and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the reply instruction of the second instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thesecond instruction, and when XX is any value except 01, it indicatesthat the communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect,communicating, by the power supply device, with the terminal device todetermine the charging current of the quick charging mode comprises:receiving, by the power supply device, a third instruction from theterminal device, wherein the third instruction indicates a maximumcharging current currently supported by the terminal device; andtransmitting, by the power supply device, a reply instruction of thethird instruction to the terminal device, wherein the reply instructionof the third instruction indicates that the power supply device hasreceived the third instruction, or the third instruction indicates thatthe terminal device is ready to enter the constant current phase.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the third instruction is 101010YYY000, Y indicates 1 bit, and themaximum charging current currently supported by the terminal deviceequals to 3000+(YYY*250) mA.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the reply instruction of the third instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thethird instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect,communicating, by the power supply device, with the terminal device toconstantly receive the information of the voltage of the battery fromthe terminal device comprises: receiving, by the power supply device, afourth instruction from the terminal device, wherein the fourthinstruction indicates the voltage of the battery; and transmitting, bythe power supply device, a reply instruction of the fourth instructionto the terminal device, wherein the reply instruction of the fourthinstruction indicates that the power supply device has received thefourth instruction.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and thevoltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, thereply instruction of the fourth instruction further indicates that theUSB interface is in bad contact, or indicates that the impedance of thecharge circuit between the power supply device and the terminal deviceis abnormal, and is ready to exit the quick charging mode, or indicatesthat the quick charging communication process needs to be reactivated.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the reply instruction of the fourth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefourth instruction, XX=11 indicates that the USB interface is in badcontact, or indicates that the impedance of the charge circuit betweenthe power supply device and the terminal device is abnormal, and isready to exit the quick charging mode, or indicates that the quickcharging communication process needs to be reactivated, and when XX isany value except 01 and 11, it indicates that the communication betweenterminal device and the power supply device becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, themethod further comprises: receiving, by the power supply device, a fifthinstruction from the terminal device, wherein the fifth instructionindicates a maximum voltage of the battery; and transmitting, by thepower supply device, a reply instruction of the fifth instruction to theterminal device, wherein the reply instruction of the fifth instructionindicates that the power supply device has received the fifthinstruction.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and themaximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, a formatof the reply instruction of the fifth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefifth instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, themethod further comprises: executing, by the power supply device, atleast one of following operations when the communication between thepower supply device and the terminal device becomes abnormal, whereinthe following operations comprise: exiting the quick charging mode,charging the battery in the normal charging mode, stopping charging, orreactivating the quick charging communication process.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, aninstruction received from the terminal device by the power supply devicecomprises multiple bits, when the power supply device receives anyinstruction, the power supply device firstly receives a MSB of themultiple bits of the any instruction; or an instruction transmitted fromthe power supply device to the terminal device comprises multiple bits,when the power supply device transmits an instruction, the power supplydevice firstly transmits a MSB of the multiple bits of the instruction.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, clocksignals used in the communication between the power supply device andthe terminal device are provided by the power supply device.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, aninstruction transmitted from the power supply device to the terminaldevice comprises multiple bits, during a process of transmitting each ofthe multiple bits, the power supply device firstly transmits each bit,and then transmits a clock interrupt signal; or a reply instructionreceived from the terminal device by the power supply device comprisesmultiple bits, during a process of receiving each of the multiple bits,the power supply device firstly transmits the clock interrupt signal,and then receives each bit after a preset time interval.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, eachinstruction received from the terminal device by the power supply devicecomprises a 12-bit data, the power supply device receives the 12-bitdata from the terminal device via twelve continuous clock periods of theclock signal, level of previous 500 μs of each of the twelve continuousclock periods is high, and level of latter 10 μs of each of the twelvecontinuous clock periods is low; or each reply instruction transmittedfrom the power supply device to the terminal device comprises a 5-bitdata, the power supply device transmits the 5-bit data to the terminaldevice via five continuous clock periods of the clock signal, level ofprevious 10 μs of each of the five continuous clock periods is low, andlevel of latter 500 μs of each of the five continuous clock periods ishigh.

In combination with the second aspect or any of the above implementationmanners, in another implementation manner of the second aspect, during aprocess that the power supply device receives an instruction from theterminal device, a minimum value of high level of the clock signal usedbetween the power supply device and the terminal device equals to VDD ofthe power supply device minus 0.7V; or during the process that the powersupply device receives an instruction from the terminal device, amaximum value of low level of the clock signal used between the powersupply device and the terminal device is 0.8V; or during a process thatthe power supply device transmits an instruction to the terminal device,a minimum value of high level of the clock signal used between the powersupply device and the terminal device equals to 0.25VDD+0.8V; or duringthe process that the power supply device transmits an instruction to theterminal device, a maximum value of the high level of the clock signalused between the power supply device and the terminal device is 4.5V; orduring the process that the power supply device transmits an instructionto the terminal device, a maximum value of low level of the clock signalis 0.15VDD. The VDD is a work voltage of the power supply device, and/orthe VDD is greater than 3.2V and less than 4.5V.

In combination with the third aspect, in an implementation manner of thethird aspect, the first instruction further indicates path impedance ofthe terminal device, the path impedance of the terminal device isconfigured for the power supply device to determine whether the USBinterface is in good contact, or to determine whether impedance of acharge circuit between the power supply device and the terminal deviceis abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the first instruction is 101000YYYYY0, Y indicates 1 bit, and thepath impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is further configured to receive a replyinstruction of the first instruction from the power supply device, andthe reply instruction of the first instruction indicates that the powersupply device supports the quick charging mode, or indicates that thepower supply device agrees to charge the battery in the quick chargingmode.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the reply instruction of the first instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefirst instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is configured to transmit a secondinstruction to the power supply device, and the second instructionindicates that the output voltage of the power supply device is high,low, or proper. The communication control circuit is configured toreceive a reply instruction of the second instruction, and the replyinstruction of the second instruction indicates that the power supplydevice has received the second instruction.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the second instruction is 101001000YY0, Y indicates 1 bit, YY=11indicates that the output voltage of the power supply device is proper,YY=10 indicates that the output voltage of the power supply device ishigh, YY=01 indicates that the output voltage of the power supply deviceis low, and YY=00 indicates that the communication between the terminaldevice and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the reply instruction of the second instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thesecond instruction, and when XX is any value except 01, it indicatesthat the communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is configured to transmit a thirdinstruction to the power supply device, and the third instructionindicates a maximum charging current currently supported by the terminaldevice. The communication control circuit is configured to receive areply instruction of the third instruction from the power supply device,and the reply instruction of the third instruction indicates that thepower supply device has received the third instruction, or the thirdinstruction indicates that the terminal device is ready to enter theconstant current phase.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the third instruction is 101010YYY000, Y indicates 1 bit, and themaximum charging current currently supported by the terminal deviceequals to 3000+(YYY*250) mA.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the reply instruction of the third instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thethird instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is configured to constantly transmit afourth instruction to the power supply device, and the fourthinstruction indicates the voltage of the battery. The communicationcontrol circuit is configured to receive a reply instruction of thefourth instruction from the power supply device, and the replyinstruction of the fourth instruction indicates that the power supplydevice has received the fourth instruction.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and thevoltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, the replyinstruction of the fourth instruction further indicates that the USBinterface is in bad contact, or indicates that the impedance of thecharge circuit between the power supply device and the terminal deviceis abnormal, and is ready to exit the quick charging mode, or indicatesthat the quick charging communication process needs to be reactivated.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the reply instruction of the fourth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefourth instruction, XX=11 indicates that the USB interface is in badcontact, or indicates that the impedance of the charge circuit betweenthe power supply device and the terminal device is abnormal, and isready to exit the quick charging mode, or indicates that the quickcharging communication process needs to be reactivated, and when XX isany value except 01 and 11, it indicates that the communication betweenterminal device and the power supply device becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is further configured to transmit a fifthinstruction to the power supply device, and the fifth instructionindicates a maximum voltage of the battery. The communication controlcircuit is further configured to receive a reply instruction of thefifth instruction, and the reply instruction of the fifth instructionindicates that the power supply device has received the fifthinstruction.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and themaximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, a formatof the reply instruction of the fifth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefifth instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, thecommunication control circuit is further configured to execute at leastone of following operations when the communication between the powersupply device and the terminal device becomes abnormal, and thefollowing operations comprise: exiting the quick charging mode, chargingthe battery in the normal charging mode, stopping charging, orreactivating the quick charging communication process.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, aninstruction transmitted from the terminal device to the power supplydevice comprises multiple bits, when the terminal device transmits anyinstruction, the terminal device firstly transmits a most significantbit (MSB) of the multiple bits of the any instruction; or an instructionreceived from the power supply device by the terminal device comprisesmultiple bits, when the terminal device receives an instruction, theterminal device firstly receives a MSB of the multiple bits of theinstruction.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, clocksignals used in the communication between the power supply device andthe terminal device are provided by the power supply device.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, aninstruction transmitted from the power supply device to the terminaldevice comprises multiple bits, during a process of transmitting each ofthe multiple bits, the power supply device firstly transmits each bit,and then transmits a clock interrupt signal; or a reply instructionreceived from the terminal device by the power supply device comprisesmultiple bits, during a process of receiving each of the multiple bits,the power supply device firstly transmits the clock interrupt signal,and then receives each bit after a preset time interval.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, eachinstruction received from the terminal device by the power supply devicecomprises a 12-bit data, the power supply device receives the 12-bitdata from the terminal device via twelve continuous clock periods of theclock signal, level of previous 500 μs of each of the twelve continuousclock periods is high, and level of latter 10 μs of each of the twelvecontinuous clock periods is low; or each reply instruction transmittedfrom the power supply device to the terminal device comprises a 5-bitdata, the power supply device transmits the 5-bit data to the terminaldevice via five continuous clock periods of the clock signal, level ofprevious 10 μs of each of the five continuous clock periods is low, andlevel of latter 500 μs of each of the five continuous clock periods ishigh.

In combination with the third aspect or any of the above implementationmanners, in another implementation manner of the third aspect, during aprocess that the power supply device receives an instruction from theterminal device, a minimum value of high level of the clock signal usedbetween the power supply device and the terminal device equals to VDD ofthe power supply device minus 0.7V; or during the process that the powersupply device receives an instruction from the terminal device, amaximum value of low level of the clock signal used between the powersupply device and the terminal device is 0.8V; or during a process thatthe power supply device transmits an instruction to the terminal device,a minimum value of high level of the clock signal used between the powersupply device and the terminal device equals to 0.25VDD+0.8V; or duringthe process that the power supply device transmits an instruction to theterminal device, a maximum value of the high level of the clock signalused between the power supply device and the terminal device is 4.5V; orduring the process that the power supply device transmits an instructionto the terminal device, a maximum value of low level of the clock signalis 0.15VDD. The VDD is a work voltage of the power supply device, and/orthe VDD is greater than 3.2V and less than 4.5V.

In combination with the fourth aspect, in an implementation manner ofthe fourth aspect, the first instruction further indicates pathimpedance of the terminal device, the path impedance of the terminaldevice is configured for the power supply device to determine whetherthe USB interface is in good contact, or to determine whether impedanceof a charge circuit between the power supply device and the terminaldevice is abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the first instruction is 101000YYYYY0, Y indicates 1 bit, and thepath impedance of the terminal device equals to YYYYY*5mΩ.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is further configured to transmit a replyinstruction of the first instruction to the terminal device, and thereply instruction of the first instruction indicates that the powersupply device supports the quick charging mode, or indicates that thepower supply device agrees to charge the battery in the quick chargingmode.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the reply instruction of the first instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefirst instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is configured to receive a secondinstruction from the terminal device, and the second instructionindicates that the output voltage of the power supply device is high,low, or proper. The communication control circuit is configured totransmit a reply instruction of the second instruction to the terminaldevice, and the reply instruction of the second instruction indicatesthat the power supply device has received the second instruction.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the second instruction is 101001000YY0, Y indicates 1 bit, YY=11indicates that the output voltage of the power supply device is proper,YY=10 indicates that the output voltage of the power supply device ishigh, YY=01 indicates that the output voltage of the power supply deviceis low, and YY=00 indicates that the communication between the terminaldevice and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the reply instruction of the second instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thesecond instruction, and when XX is any value except 01, it indicatesthat the communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is configured to receive a thirdinstruction from the terminal device, and the third instructionindicates a maximum charging current currently supported by the terminaldevice. The communication control circuit is configured to transmit areply instruction of the third instruction to the terminal device, andthe reply instruction of the third instruction indicates that the powersupply device has received the third instruction, or the thirdinstruction indicates that the terminal device is ready to enter theconstant current phase.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the third instruction is 101010YYY000, Y indicates 1 bit, and themaximum charging current currently supported by the terminal deviceequals to 3000+(YYY*250) mA.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the reply instruction of the third instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thethird instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is configured to constantly receive afourth instruction from the terminal device, and the fourth instructionindicates the voltage of the battery. The communication control circuitis configured to transmit a reply instruction of the fourth instructionto the terminal device, and the reply instruction of the fourthinstruction indicates that the power supply device has received thefourth instruction.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the fourth instruction is 101011YYYYYY, Y indicates 1 bit, and thevoltage of the battery equals 3404+(YYYYYY*16) mV.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thereply instruction of the fourth instruction further indicates that theUSB interface is in bad contact, or indicates that the impedance of thecharge circuit between the power supply device and the terminal deviceis abnormal, and is ready to exit the quick charging mode, or indicatesthat the quick charging communication process needs to be reactivated.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the reply instruction of the fourth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefourth instruction, XX=11 indicates that the USB interface is in badcontact, or indicates that the impedance of the charge circuit betweenthe power supply device and the terminal device is abnormal, and isready to exit the quick charging mode, or indicates that the quickcharging communication process needs to be reactivated, and when XX isany value except 01 and 11, it indicates that the communication betweenterminal device and the power supply device becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is further configured to receive a fifthinstruction from the terminal device, and the fifth instructionindicates a maximum voltage of the battery. The communication controlcircuit is further configured to transmit a reply instruction of thefifth instruction to the terminal device, and the reply instruction ofthe fifth instruction indicates that the power supply device hasreceived the fifth instruction.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the fifth instruction is 101100YYYYYY, Y indicates 1 bit, and themaximum voltage of the battery is 4100+YYYYYY*10 mV.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, a formatof the reply instruction of the fifth instruction is 101XX, X indicates1 bit, XX=01 indicates that the power supply device has received thefifth instruction, and when XX is any value except 01, it indicates thatthe communication between the terminal device and the power supplydevice becomes abnormal.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, thecommunication control circuit is further configured to execute at leastone of following operations when the communication between the powersupply device and the terminal device becomes abnormal, and thefollowing operations comprise: exiting the quick charging mode, chargingthe battery in the normal charging mode, stopping charging, orreactivating the quick charging communication process.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, aninstruction received from the terminal device by the power supply devicecomprises multiple bits, when the power supply device receives anyinstruction, the power supply device firstly receives a most significantbit (MSB) of the multiple bits of the any instruction; or an instructiontransmitted from the power supply device to the terminal devicecomprises multiple bits, when the power supply device transmits aninstruction, the power supply device firstly transmits a MSB of themultiple bits of the instruction.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, clocksignals used in the communication between the power supply device andthe terminal device are provided by the power supply device.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, aninstruction transmitted from the power supply device to the terminaldevice comprises multiple bits, during a process of transmitting each ofthe multiple bits, the power supply device firstly transmits each bit,and then transmits a clock interrupt signal; or a reply instructionreceived from the terminal device by the power supply device comprisesmultiple bits, during a process of receiving each of the multiple bits,the power supply device firstly transmits the clock interrupt signal,and then receives each bit after a preset time interval.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, eachinstruction received from the terminal device by the power supply devicecomprises a 12-bit data, the power supply device receives the 12-bitdata from the terminal device via twelve continuous clock periods of theclock signal, level of previous 500 μs of each of the twelve continuousclock periods is high, and level of latter 10 μs of each of the twelvecontinuous clock periods is low; or each instruction transmitted fromthe power supply device to the terminal device comprises a 5-bit data,the power supply device transmits the 5-bit data to the terminal devicevia five continuous clock periods of the clock signal, level of previous10 μs of each of the five continuous clock periods is low, and level oflatter 500 μs of each of the five continuous clock periods is high.

In combination with the fourth aspect or any of the above implementationmanners, in another implementation manner of the fourth aspect, during aprocess that the power supply device receives an instruction from theterminal device, a minimum value of high level of the clock signal usedbetween the power supply device and the terminal device equals to VDD ofthe power supply device minus 0.7V; or during the process that the powersupply device receives an instruction from the terminal device, amaximum value of low level of the clock signal used between the powersupply device and the terminal device is 0.8V; or during a process thatthe power supply device transmits an instruction to the terminal device,a minimum value of high level of the clock signal used between the powersupply device and the terminal device equals to 0.25VDD+0.8V; or duringthe process that the power supply device transmits an instruction to theterminal device, a maximum value of the high level of the clock signalused between the power supply device and the terminal device is 4.5V; orduring the process that the power supply device transmits an instructionto the terminal device, a maximum value of low level of the clock signalused between the power supply device and the terminal device is 0.15VDD.The VDD is a work voltage of the power supply device, and/or the VDD isgreater than 3.2V and less than 4.5V.

The technical solution of implementations of the present disclosure willbe described clearly and completely in combination with the accompanyingdrawings of the implementations of the present disclosure. Obviously,the described implementations are a part of implementations of thepresent disclosure, and not all of the implementations. According to theimplementations of the present disclosure, other implementationsobtained by those skilled in the art without creative work all fallwithin the protection scope of the present disclosure.

FIG. 1 is a schematic diagram illustrating a charging process inaccordance with an implementation of the present disclosure.

As illustrated by FIG. 1, a charging communication process may includefive phases. The charging communication process may generally refer to acharging communication process in which a charging mode having a greatcharging speed is adopted. Hereinafter, for the sake of easyunderstanding, the charging communication process may be referred as aquick charging communication process. The quick charging communicationprocess may be conducted between a power supply device such as a poweradapter and a terminal device such as a mobile phone, a tablet computerand the like.

Phase 1:

A terminal device can detect a type of a power supply device via apositive data (D+) line and a negative data (D−) line. When it isdetermined that the power supply device is a non-USB charging device, acurrent absorbed by the terminal device can be greater than a presetcurrent threshold I2. When the power supply device determines thatwithin a preset time length (for example, continuous T1 time length) anoutput current of the power supply device is greater than or equal toI2, the power supply device determines that the terminal device hasrecognized the type of the power supply device, and the power supplydevice activates a handshake communication between the power supplydevice and the terminal device. The power supply device transmits afirst instruction to query whether the terminal device agrees toactivate a first charging mode. The terminal device can be charged inthe first charging mode and a second charging mode. A charging speed ofthe first charging mode is greater than that of the second chargingmode. That is to say, the time consumed by charging the terminal devicein the first charging mode is less than that consumed by charging theterminal device in the second charging mode. Hereinafter, for the sakeof easy understanding, the first charging mode may be referred as aquick charging mode, and the second charging mode may be referred as anormal charging mode.

When a reply instruction received from the terminal device by the powersupply device indicates that the terminal device disagrees to activatethe quick charging mode, the power supply device redetects the outputcurrent of the power supply device. When the output current of the powersupply device is still greater than or equal to I2, the power supplydevice retransmits the request to query whether the terminal device isto activate the quick charging mode, and the above steps of the phase 1are repeated until the terminal device agrees to activate the quickcharging mode or the output current of the power supply device is nolonger greater than or equal to I2.

When the terminal device agrees to activate quick charging, the quickcharging communication process enters a phase 2.

Phase 2:

The power supply device can output different voltage levels. The powersupply device transmits a second instruction to the terminal device toquery the terminal device for whether an output voltage of the powersupply device is proper (that is, whether the output voltage is properto be a charging voltage of the quick charging mode).

The terminal device transmits a reply to the power supply device toinform the power supply device that the output voltage of the powersupply device is high, low, or proper. If the reply the power supplydevice received from the terminal device indicates that the outputvoltage of the power supply device is high or low, the power supplydevice selects another output voltage level, and retransmits the secondinstruction to the terminal device to re-query the terminal device forwhether the output voltage of the power supply device is proper.

The above steps of the phase 2 are repeated until the terminal devicereturns a reply to the power supply device to inform the power supplydevice that the output voltage of the power supply device is proper, andthe quick charging communication process enters a phase 3.

Phase 3:

The power supply device transmits a third instruction to the terminaldevice to query a maximum charging current currently supported by theterminal device. The terminal device transmits a reply to the powersupply device to inform the power supply device of the maximum chargingcurrent currently supported by the terminal device, and the quickcharging communication process enters a phase 4.

Phase 4:

The power supply device sets the output current of the power supplydevice to be the maximum charging current currently supported by theterminal device, and the quick charging communication process enters aconstant current phase, that is, a phase 5.

Phase 5:

After entering the constant current phase, the power supply devicetransmits a fourth instruction every a time interval to query a currentvoltage of a battery of the terminal device. The terminal device cantransmit a reply to the power supply device to inform the power supplydevice of the current voltage of the battery of the terminal device. Thepower supply device can determine whether a USB interface is in goodcontact and whether it is needed to decrease the current chargingcurrent value of the terminal device according to the reply forindicating the current voltage of the battery of the terminal device.When the power supply device determines that the USB interface is in badcontact, the power supply device transmits a fifth instruction to theterminal device, and then resets to reenter the phase 1.

It can be understood that in the constant current phase the outputcurrent of the power supply device does not keep unchanged all the time.The constant current phase is a multi-stage constant current phase, andthe output current of the power supply device keeps unchanged within aperiod, i.e., in the constant current phase, multiple constant currentcharging stages corresponding to different charging currents areconducted successively.

For the above quick communication process applied between the powersupply device and the terminal device, a quick charging communicationinstruction set applied between the power supply device and the terminaldevice can be defined. For example, the quick charging communicationinstruction set is illustrated by FIG. 1.

TABLE 1 Quick charging communication instruction set Instruction 1:requesting for quick charging Power supply 10101000 0xA8device−>Terminal device Terminal 101XYYYYYY X: 1−>Agree 0−>Disagree,device−>Power Path impedance = supply device YYYYYY*5(mΩ) Instruction 2:querying whether a voltage of the power supply device is proper Powersupply 10100100 0xA4 device−>Terminal device Terminal 1010XX0000 XX:11−>Proper 10−>High device−>Power 01−>Low 00−>Error supply deviceInstruction 3: querying for a maximum charging current currentlysupported by the terminal device Power supply 10100110 0xA6device−>Terminal device Terminal 1010XXXXXX Maximum charging currentdevice−>Power currently supported supply device by the terminal device =3000 + (XXXXXX*250)(mA) Instruction 4: querying for a current voltage ofa battery of the terminal device Power supply 10100010 0xA2device−>Terminal device Terminal 101XYYYYYY X: 1−>Being chargeddevice−>Power 0−>Uncharged, Battery supply device voltage = 3404 +(YYYYYY*16)(mV) Instruction 5: informing the terminal device that USBconnection is poor and quick charging should be stopped Power supply10110010 0xB2 device−>Terminal device Terminal NONE device−>Power supplydevice

From table 1, it can be seen that for each communication the powersupply device first transmits an 8-bit data, and then the terminaldevice returns a 10-bit data. When the power supply device transmits adata, the power supply device can firstly transmit a most significantbit (MSB). Similarly, when the power supply device receives a data, thepower supply device first receives a MSB. Clock signals for datatransmission and data reception of the power supply device can beprovided by the power supply device.

When the power supply device transmits a data, the power supply devicetransmits each bit of the data before transmitting a clock interruptsignal, which can guarantee the accuracy of the data received by theterminal device. When the power supply device receives a data, the powersupply device can first transmit the clock interrupt signal, and thenreceive each bit of the data after a certain time, which can guaranteethe accuracy and reliability of the data received by the power supplydevice.

FIG. 2 is a schematic view illustrating that the power supply deviceimplements a data reception and data transmission in accordance with animplementation of the present disclosure. For FIG. 2, there are a numberof methods for parsing a data to determine whether the data is valid.For example, previous n bits of a data can be defined as 101 in advance.When previous 3 bits of a data received by the power supply device isnot 101, the data is determined as an invalid data, and communicationfails. Or, a received data is defined to include 10 bits in advance. Ifa received data does not include 10 bits, the received data isdetermined as an invalid data, and communication fails.

FIG. 3 is a schematic view of a communication sequence of the powersupply device in accordance with an implementation of the presentdisclosure. From FIG. 3, a relationship between a communication sequenceindicated by the clock signals which are transmitted by the D+ data lineand data signals transmitted by the D− data line. FIG. 4 illustrates adetailed example. In FIG. 4, after the power supply device transmits theinstruction 10101000 to the terminal device, the power supply devicereceives the reply instruction 1011001111 from the terminal device.

The above quick charging communication process is finished based onnegotiation between the power supply device and the terminal device, andsafety of quick charging can be ensured.

From the above, it can be seen that during the whole process, the powersupply device acts as a host, and conducts a handshake communicationwith the terminal device actively. The power supply device firstlydetermines whether to activate the quick charging communication process.After activating the quick charging communication process, the powersupply device transmits an instruction to the terminal device actively.A condition that causes the power supply device to determine to activatethe quick charging process is that the power supply device determinesthat within the preset time period the output current of the powersupply device is greater than or equal to I2. When the power supplydevice determines that the condition is satisfied, the power supplydevice determines that the terminal device has recognized the type ofthe power supply device, that is, determines that the terminal devicehas recognized that the power supply device is a non-USB charging device(or has recognized that the power supply device is a standard chargingdevice, and is not a non-standard charging device, such as a computer,or has recognized that the power supply device is not a computer, thatis, the non-USB charging device can refer to any other charging deviceexcept a computer). By means of such a detection manner, the powersupply device can be acted as a host, and the quick chargingcommunication process is simplified. However, this manner is similar toa blind detection manner, that is, the power supply device guesses thatthe terminal device has recognized the type of the power supply device.Adopting the blind detection manner, certain errors may occur. Forexample, if a standard charging current of some terminal devices is I2(or about I2), the current detected by the power supply device may notbe exactly right, and the power supply device determines that thecharging current of such terminal devices is less than I2, which mayresult in that such terminal devices cannot activate quick chargingcommunication all the time and have to adopt a standard charging methodfor charging.

To avoid the above problem, the following will illustrate a quickcharging method in accordance with another implementation of the presentdisclosure in combination with FIG. 5. In an implementation illustratedby FIG. 5, the quick communication process between the terminal deviceand the power supply device is activated by the terminal device, thatis, the terminal device actively transmits a quick charging request tothe power supply device. What needs to be illustrated is that after theterminal device transmits the quick charging request, the subsequentprocess can be still the same as the process illustrated by FIGS. 1-4.That is, the power supply device actively activates the quick chargingcommunication with the terminal device to query a voltage, a current,and other parameters of the quick charging. Or, after the terminaldevice activates the quick charging, in the subsequent communicationprocess the terminal device actively transmits instructions to the powersupply device, that is, the terminal device actively provides theterminal device with the voltage of the battery, the maximum chargingcurrent currently supported by the terminal device, and so on. The powersupply device may do not reply, or simply reply that the power supplydevice has received the instruction, the power supply device does notreceive the instruction, or the power supply device agrees or disagrees.What needs to be further illustrated is that the quick chargingcommunication instruction set and the communication sequencerelationship illustrated by the above (for example, table 1, FIGS. 2-4)can be still applied in the implementations that the terminal deviceactively activates the quick charging request directly or after simplevariation. For example, after the terminal device activates the quickcharging request, if the subsequent communication process is stillactivated by the power supply device (in the subsequent phases of thequick charging process the power supply device actively activates thehandshake request, that is, actively transmits the above instructions2-5), the above instructions 2-5 can be still used, and the terminaldevice transmits the instruction 1. If the subsequent communicationprocess is finished by the terminal device, an instruction set suitablefor that the terminal device actively initiates the communication can bedefined. The instruction set illustrated by FIG. 2 can be used.

TABLE 2 Quick charging communication instruction set Instruction typeInstruction format Instruction illustration Fourth instrution□tell_volt□Terminal 101011YYYYYY Battery voltage = 3404 + device−>Power (YYYYYY *16) supply device Power supply 101XX XX□01−>Received□11−>device−>Terminal USB contact is not good, device impedance is too high;other formats−>abnormal communication Secondinstruction□tell_is_vbus_ok□ Terminal 101001000YY0 YY: 11−>an outputvoltage of device−>Power the power supply device is supply deviceproper; 10−>the output voltage of the power supply device is too high;01−> the output voltage of the power supply device is too low;00−>abnormal communication Power supply 101XX XX: 01−>Received□Otherdevice−>terminal formats−>abnormal device communication Firstinstrution□tell_fastchg_ornot□ Terminal 101000YYYYY0 R = YYYYY*5device−>Power supply device Power supply 101XX XX: 01−>Received□Otherdevice−>Terminal formats−>Abnormal device communication Thirdinstruction□tell_adapter_current_level□ Terminal 101010YYY000 Maximumcharging current device>Power supply currently supported by the deviceterminal device = 3000 + (YYY * 250) Power supply 101XX XX:01−>Received; Other device−>Terminal formats −>Abnormal devicecommunication Fifth instruction□tell_adapter_battery_max_volt□ Terminal101100YYYYYY Maximum voltage of the device−>Power battery = 4100 +supply device (YYYYYY * 10) Power supply 101XX XX□01−>Received; Otherdevice−>Terminal formats−>Abnormal device communication

What needs to be illustrated is that in the above table 3404 is 3404 mV(3.404V), 4100 is 4100 mV (4.1V), 3000 is 3000 mA (3A), and 250 is 250mA (0.25 A).

Certainly, after the terminal device actively initiates the quickcharging request, in the subsequent communication process the terminaldevice and the power supply device can be respectively in charge ofinitiation work of some of the communication process. For example, thepower supply device actively queries the terminal device for whether theoutput voltage is proper, the terminal device actively provides thepower supply device with the battery voltage, and so on. In FIG. 5, fromthe perspective of the terminal device, the terminal device activelytransmitting an instruction to the power supply device is taken as anexample for illustration. It can be understood that steps or operationsillustrated by FIG. 5 are just examples. The implementations of thepresent disclosure can further execute other steps or variations of thesteps of FIG. 5. In addition, the steps of FIG. 5 can be executed inother sequences different from the sequence of FIG. 5, and furthermoresome of the operations of FIG. 5 may not be executed.

FIG. 5 includes the follows.

A: the terminal device recognizes a type of the power supply device whenthe power supply device is coupled to the terminal device.

When it is detected that the coupling device is a USB device, itindicates that the coupling device is not a specified adapter, and maybe a computer.

B: the terminal device determines whether the self status satisfies aquick charging condition. When the self status satisfies the quickcharging condition, an operation at C is executed, otherwise anoperation at D is executed.

C: when the terminal device detects that self status satisfies the quickcharging condition, the terminal device transmits an instruction 1(corresponding to the first instruction described above) via D+ and/orD− to initiate the quick charging request.

D: if the self status does not satisfy the quick charging condition, forexample, when the remaining capacity of the battery is great, or theinterior temperature of the terminal device is not proper for quickcharging, the terminal device may not transmit the quick chargingrequest, and is charged in a standard charging mode (corresponding tothe normal charging mode described above).

E: the terminal device determines whether a reply instruction of theinstruction 1 which indicates whether the power supply device supports aquick charging mode is received, and the reply instruction of theinstruction 1 indicates whether the power supply device supports thequick charging mode. When the reply instruction of the instruction 1 isreceived, an operation at F is executed, otherwise the operation at D isexecuted.

When the power supply device supports the quick charging mode, theoperation at F is executed. When the power supply device does notsupport the quick charging mode or the communication becomes abnormal(for example, the reply instruction of the instruction 1 is notreceived), the terminal device is charged in the standard charging mode.

F: the terminal device transmits an instruction 2 to the power supplydevice to inform the power supply device that the current output voltageis high, low, or proper.

The power supply device can output different voltage levels. When thepower supply device receives the instruction 2, the power supply deviceoutputs another voltage level according to the instruction 2 until thereceived instruction 2 indicates that the output voltage of the powersupply device is proper.

Optionally, in an implementation, the instruction 2 can indicate thecurrent battery voltage, so as to cause the power supply device toadjust the output voltage according to the battery voltage.Specifically, a mapping relationship between battery voltages andcharging voltages of the quick charging mode can be establishedbeforehand. In actual use, the power supply device can determine thevoltage of quick charging corresponding to the current battery voltageaccording to the mapping relationship, and then the power supply deviceadjusts the output voltage to be the voltage of the quick charging.

G: the terminal device determines whether the reply instruction of theinstruction 2 from the power supply device is received. When the replyinstruction of the instruction 2 is received, an operation at H isexecuted, otherwise the operation at D is executed.

The operation at G is an optional operation. The reply instruction ofthe instruction 2 can indicate that the power supply device has receivedthe instruction 2, or the power supply device has adjusted the outputvoltage according to the battery voltage.

H: the power supply device transmits an instruction 3 to the powersupply device.

The instruction 3 can indicates a maximum charging current currentlysupported by the terminal device. After the power supply device receivesthe instruction 3, the power supply device can reply that theinstruction 3 has been received.

I: the quick charging is activated and the charging process enters aconstant current phase.

J: the terminal device constantly transmits an instruction 4 to thepower supply device to inform the power supply device of the batteryvoltage, so as to cause the power supply device to finish impedancedetection and adjustment of constant current.

The power supply device can transmit an instruction 4 to the powersupply device in a certain period. Or, the terminal device can transmitthe instruction 4 in a preset mode, and the preset mode is establishedaccording to charging characteristics of the battery.

In addition, the power supply device can be requested to transmit areply each time the instruction 4 is received. If the terminal devicedoes not receive a reply, the terminal device determines that thecommunication becomes abnormal, and the terminal device is charged inthe standard charging mode.

K: the terminal device determines whether a reply instruction of theinstruction 4 which indicates whether the power supply device hasreceived the instruction 4 is received. When the reply instruction ofthe instruction 4 is received, step L is executed, otherwise theoperation at D is executed.

L: the power supply device computes path impedance according to thebattery voltage and adjusts constant current.

In the implementation of the present disclosure, after the terminaldevice recognizes the type of the power supply device, the terminaldevice actively initiates the quick charging request, thus the wholequick charging process is reliable and reasonable.

In combination with FIGS. 6-7, the following will specifically describethe terminal device and the power supply device of the implementationsof the present disclosure. It can be understood that the terminal deviceof FIG. 6 can implement various functions described in the quickcharging method, and the power supply device of FIG. 7 can implementvarious functions described in the quick charging method. To avoidrepetition, detailed description will be omitted.

FIG. 6 is a schematic diagram illustrating a terminal device inaccordance with an implementation of the present disclosure. A terminaldevice 600 of FIG. 6 is coupled to a power supply device via a USBinterface. Power lines of the USB interface are used for charging abattery of the terminal device 600. Data lines of the USB interface areused for communication between the terminal device 600 and the powersupply device. The terminal device 600 supports a normal charging modeand a quick charging mode. A charging speed of the quick charging modeis greater than that of the normal charging mode. The terminal device600 includes a communication control circuit 610 and a charging circuit620. It shall be noted that the terminal device 600 may be implementedin the form of one or more processors and a computer readable memory.The computer readable memory stores one or more instructions thereinwhich may be invoked by the one or more processors to realize functionsrealized by the communication control circuit 610 and the chargingcircuit 620.

The communication control circuit 610 is configured to determine tocharge the battery of the terminal device in the quick charging modebased on that current status of the terminal device satisfies acondition that the battery of the terminal device is operable to becharged in the quick charging mode by the power supply device,communicate with the power supply device to determine a charging voltageor a charging current of the quick charging mode, and communicate withthe power supply device to transmit information of a current voltage ofthe battery to the power supply device after the power supply deviceadjusts an output voltage or output current of the power supply deviceaccording to the charging voltage or the charging current of thecharging mode and enters a constant current phase, so as to cause thepower supply device to adjust the output current according to thecurrent voltage of the battery. An implementation is the follows. Thecommunication control circuit 610 is configured to determine a type ofthe power supply device when it is detected that the power supply deviceis coupled to the terminal device 600, activate a quick chargingcommunication process between the terminal device 600 and the powersupply device when it is determined that the power supply device is anon-USB power supply device, and transmit a first instruction to thepower supply device, and the first instruction is configured to requestthe power supply device to charge the battery in the quick chargingmode. The communication control circuit 610 is further configured tocommunicate with the power supply device to determine a charging voltageof the quick charging mode, communicate with the power supply device todetermine a charging current of the quick charging mode, and communicatewith the power supply device to constantly transmit information of avoltage of the battery to the power supply device when the power supplydevice adjusts an output voltage and output current of the power supplydevice to be the charging voltage and the charging current of the quickcharging mode respectively and enters a constant current phase, so as tocause the power supply device to adjust the output current according tothe voltage of the battery, and charge the battery in a multi-stageconstant current mode via the charging circuit 620.

In implementations of the present disclosure, the power supply devicedoes not increase the charging current blindly for quick charging, butnegotiates with the terminal device via communication with the terminaldevice 600 to determine whether the quick charging mode can be adopted.Compared with the present technology, the security of the quick chargingprocess is improved.

In an alternative implementation, the first instruction furtherindicates path impedance of the terminal device 600. The path impedanceof the terminal device 600 is configured for the power supply device todetermine whether the USB interface is in good contact, or whetherimpedance of a charge circuit between the power supply device and theterminal device 600 is abnormal.

In an alternative implementation, a format of the first instruction is101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminaldevice 600 equals to YYYYY*5mΩ.

In an alternative implementation, the communication control circuit 610is further configured to receive a reply instruction of the firstinstruction from the power supply device, and the reply instruction ofthe first instruction indicates that the power supply device supportsthe quick charging mode, or that the power supply device agrees tocharge the battery in the quick charging mode.

In an alternative implementation, a format of the reply instruction ofthe first instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the first instruction, and when XXis any value except 01, it indicates that the communication between theterminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610is configured to transmit a second instruction to the power supplydevice, and the second instruction indicates that the output voltage ofthe power supply device is high, low, or proper. The communicationcontrol circuit 610 is configured to receive a reply instruction of thesecond instruction, and the reply instruction of the second instructionindicates that the power supply device has received the secondinstruction.

In an alternative implementation, a format of the second instruction is101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltageof the power supply device is proper, YY=10 indicates that the outputvoltage of the power supply device is high, YY=01 indicates that theoutput voltage of the power supply device is low, and YY=00 indicatesthat the communication between the terminal device 600 and the powersupply device becomes abnormal.

In an alternative implementation, a format of the reply instruction ofthe second instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the second instruction, and when XXis any values except 01, it indicates that the communication between theterminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610is configured to transmit a third instruction to the power supplydevice, and the third instruction indicates a maximum charging currentcurrently supported by the terminal device 600. The communicationcontrol circuit 610 is configured to receive a reply instruction of thethird instruction from the power supply device, and the replyinstruction of the third instruction indicates that the power supplydevice has received the third instruction, or the third instructionindicates that the terminal device 600 is ready to enter the constantcurrent phase.

In an alternative implementation, a format of the third instruction is101010YYY000, and Y indicates 1 bit. The maximum charging currentcurrently supported by the terminal device 600 equals to 3000+(YYY*250)mA.

In an alternative implementation, a format of the reply instruction ofthe third instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the third instruction, and when XXis any value except 01, it indicates that the communication between theterminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610is configured to constantly transmit a fourth instruction to the powersupply device, and the fourth instruction indicates the current voltageof the battery. The communication control circuit 610 is configured toreceive a reply instruction of the fourth instruction from the powersupply device, and the reply instruction of the fourth instructionindicates that the power supply device has received the fourthinstruction.

In an alternative implementation, a format of the fourth instruction is101011YYYYYY, and Y indicates 1 bit. The voltage of the battery equals3404+(YYYYYY*16) mV.

In an alternative implementation, the reply instruction of the fourthinstruction further indicates that the USB interface is in bad contact,or indicates that impedance of the charge circuit between the powersupply device and the terminal device 600 is abnormal, and is ready toexit the quick charging mode, or indicates that the quick chargingcommunication process needs to be reactivated.

In an alternative implementation, a format of the reply instruction ofthe fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the fourth instruction, XX=11indicates that the USB interface is in bad contact, or indicates thatthe impedance of the charge circuit between the power supply device andthe terminal device 600 is abnormal, and is ready to exit the quickcharging mode, or indicates that the quick charging communicationprocess needs to be reactivated, and when XX is any value except 01 and11, it indicates that the communication between terminal device 600 andthe power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610is further configured to transmit a fifth instruction to the powersupply device, and the fifth instruction indicates a maximum voltage ofthe battery. The communication control circuit 610 is further configuredto receive a reply instruction of the fifth instruction, and the replyinstruction of the fifth instruction indicates that the power supplydevice has received the fifth instruction.

In an alternative implementation, a format of the fifth instruction is101100YYYYYY, and Y indicates 1 bit. The maximum voltage of the batteryis 4100+YYYYYY*10 mV.

In an alternative implementation, a format of the reply instruction ofthe fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the fifth instruction, and when XXis any value except 01, it indicates that the communication between theterminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 610is further configured to execute at least one of following operationswhen the communication between the power supply device and the terminaldevice 600 becomes abnormal, and the following operations include:exiting the quick charging mode, charging the battery in the normalcharging mode, stopping charging, or reactivating the quick chargingcommunication process.

In an alternative implementation, an instruction transmitted from theterminal device 600 to the power supply device contains multiple bits.When the terminal device 600 transmits any instruction, the terminaldevice 600 first transmits a MSB of the multiple bits of the anyinstruction. Or, an instruction received from the power supply device bythe terminal device 600 contains multiple bits. When the terminal device600 receives a certain instruction, the terminal device 600 firstreceives a MSB of the multiple bits of the certain instruction.

In an alternative implementation, clock signals used in thecommunication between the power supply device and the terminal device600 are provided by the power supply device.

In an alternative implementation, an instruction transmitted from thepower supply device to the terminal device 600 contains multiple bits.During a process of transmitting each of the multiple bits, the powersupply device first transmits each bit, and then transmits a clockinterrupt signal. Or, a reply instruction received from the terminaldevice 600 by the power supply device contains multiple bits. During aprocess of receiving each of the multiple bits, the power supply devicefirst transmits the clock interrupt signal, and then receives each bitafter a preset time interval.

In an alternative implementation, each instruction received from theterminal device 600 by the power supply device contains a 12-bit data.The power supply device receives the 12-bit data from the terminaldevice 600 via twelve continuous clock periods of the clock signal.Level of previous 500 μs of each of the twelve continuous clock periodsis high, and level of latter 10 μs of each of the twelve continuousclock periods is low. Or, each reply instruction transmitted from thepower supply device to the terminal device 600 contains a 5-bit data.The power supply device transmits the 5-bit data to the terminal device600 via five continuous clock periods of the clock signal. Level ofprevious 10 μs of each of the five continuous clock periods is low, andlevel of latter 500 μs of each of the five continuous clock periods ishigh.

In an alternative implementation, during a process that the power supplydevice receives an instruction from the terminal device 600, a minimumvalue of high level of the clock signal used between the power supplydevice and the terminal device 600 equals to VDD of the power supplydevice minus 0.7V. Or, during the process that the power supply devicereceives an instruction from the terminal device 600, a maximum value oflow level of the clock signal used between the power supply device andthe terminal device 600 is 0.8V. Or, during a process that the powersupply device transmits an instruction to the terminal device 600, aminimum value of high level of the clock signal used between the powersupply device and the terminal device 600 equals to 0.25VDD+0.8V. Or,during the process that the power supply device transmits an instructionto the terminal device 600, a maximum value of the high level of theclock signal used between the power supply device and the terminaldevice 600 is 4.5V. Or, during the process that the power supply devicetransmits an instruction to the terminal device 600, a maximum value oflow level of the clock signal used between the power supply device andthe terminal device 600 is 0.15VDD. The VDD is a work voltage of thepower supply device, and/or the VDD is greater than 3.2V and less than4.5V.

FIG. 7 is a schematic diagram illustrating a power supply device inaccordance with an implementation of the present disclosure. A powersupply device 700 of FIG. 7 is coupled to a terminal device via a USBinterface. Power lines of the USB interface are used for the powersupply device 700 to charge a battery of the terminal device. Data linesof the USB interface are used for communication between the power supplydevice 700 and the terminal device. The power supply device 700 supportsa normal charging mode and a quick charging mode. A charging speed ofthe quick charging mode is greater than that of the normal chargingmode. The power supply device 700 includes a communication controlcircuit 710 and a charging circuit 720. It shall be noted that the powersupply device 700 may be implemented in the form of one or moreprocessors and a computer readable memory. The computer readable memorystores one or more instructions therein which may be invoked by the oneor more processors to realize functions realized by the communicationcontrol circuit 710 and the charging circuit 720.

The communication control circuit 710 is configured to determine tocharge the battery of the terminal device in the quick charging modebased on that current status of the terminal device satisfies acondition that the battery of the terminal device is operable to becharged in the quick charging mode, communicate with the terminal deviceto determine a charging voltage or a charging current of the quickcharging mode, adjust an output voltage or output current output to theterminal device according to the charging voltage or the chargingcurrent of the quick charging mode to enter a constant current phase,communicate with the terminal device during the constant current phaseto receive information of a current voltage of the battery, and adjuststhe output current output to the terminal device according to thecurrent voltage of the battery in the constant current phase. Animplementation is the follows. The communication control circuit 710 isconfigured to receive a first instruction from the terminal device whenthe terminal device determines that the power supply device 700 is anon-USB power supply device, and activates quick charging communicationbetween the power supply device 700 and the terminal device, and thefirst instruction requests the power supply device 700 to charge thebattery in the quick charging mode. The communication control circuit710 is further configured to communicate with the terminal device todetermine a charging voltage of the quick charging mode, communicatewith the terminal device to determine a charging current of the quickcharging mode, and adjust an output voltage and output current of thepower supply device 700 to be the charging voltage and the chargingcurrent of the quick charging mode respectively to enter a constantcurrent phase, communicate with the terminal device during the constantcurrent phase to constantly receive information of a current voltage ofthe battery from the terminal device, adjust the output currentaccording to the voltage of the battery, and charge the battery in amulti-stage constant current mode via the charging circuit 720.

In implementations of the present disclosure, the power supply devicedoes not increase the charging current blindly for quick charging, butnegotiates with the terminal device via communication with the terminaldevice 600 to determine whether the quick charging mode can be adopted.The security of the quick charging process is improved.

In an alternative implementation, the first instruction furtherindicates path impedance of the terminal device. The path impedance ofthe terminal device is configured for the power supply device 700 todetermine whether the USB interface is in good contact, or whetherimpedance of a charge circuit between the power supply device 700 andthe terminal device is abnormal.

In an alternative implementation, a format of the first instruction is101000YYYYY0, Y indicates 1 bit, and the path impedance of the terminaldevice equals to YYYYY*5mΩ.

In an alternative implementation, the communication control circuit 710is further configured to transmit a reply instruction of the firstinstruction to the terminal device, and the reply instruction of thefirst instruction indicates that the power supply device 700 supportsthe quick charging mode, or indicates that the power supply device 700agrees to charge the battery in the quick charging mode.

In an alternative implementation, a format of the reply instruction ofthe first instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device 700 has received the first instruction, and whenXX is any value except 01, it indicates that the communication betweenthe terminal device 600 and the power supply device becomes abnormal.

In an alternative implementation, the communication control circuit 710is configured to receive a second instruction from the terminal device,and the second instruction indicates whether the output voltage of thepower supply device is proper. The communication control circuit 710 isconfigured to transmit a reply instruction of the second instruction tothe terminal device, and the reply instruction of the second instructionindicates that the power supply device 700 has received the secondinstruction.

In an alternative implementation, a format of the second instruction is101001000YY0, Y indicates 1 bit, YY=11 indicates that the output voltageof the power supply device 700 is proper, YY=10 indicates that theoutput voltage of the power supply device 700 is high, YY=01 indicatesthat the output voltage of the power supply device 700 is low, and YY=00indicates that the communication between the terminal device and thepower supply device 700 becomes abnormal.

In an alternative implementation, a format of the reply instruction ofthe second instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device has received the second instruction, and when XXis any value except 01, it indicates that the communication between theterminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710is configured to receive a third instruction from the terminal device,and the third instruction indicates a maximum charging current currentlysupported by the terminal device. The communication control circuit 710is configured to transmit a reply instruction of the third instructionto the terminal device, and the reply instruction of the thirdinstruction indicates that the power supply device 700 has received thethird instruction, or the third instruction indicates that the terminaldevice is ready to enter the constant current phase.

In an alternative implementation, a format of the third instruction is101010YYY000, and Y indicates 1 bit. The maximum charging currentcurrently supported by the terminal device equals to 3000+(YYY*250) mA.

In an alternative implementation, a format of the reply instruction ofthe third instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device 700 has received the third instruction, and whenXX is any value except 01, it indicates that the communication betweenthe terminal device and the power supply device 700 become abnormal.

In an alternative implementation, the communication control circuit 710is configured to constantly receive a fourth instruction from theterminal device, and the fourth instruction indicates the voltage of thebattery. The communication control circuit 710 is configured to transmita reply instruction of the fourth instruction to the terminal device,and the reply instruction of the fourth instruction indicates that thepower supply device 700 has received the fourth instruction.

In an alternative implementation, a format of the fourth instruction is101011YYYYYY, and Y indicates 1 bit. The voltage of the battery equals3404+(YYYYYY*16) mV.

In an alternative implementation, the reply instruction of the fourthinstruction further indicates that the USB interface is in bad contact,or indicates that the impedance of the charge circuit between the powersupply device 700 and the terminal device is abnormal, and is ready toexit the quick charging mode, or indicates that the quick chargingcommunication process needs to be reactivated.

In an alternative implementation, a format of the reply instruction ofthe fourth instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device 700 has received the fourth instruction, XX=11indicates that the USB interface is in bad contact, or indicates thatthe impedance of the charge circuit between the power supply device 700and the terminal device is abnormal, and is ready to exit the quickcharging mode, or indicates that the quick charging communicationprocess needs to be reactivated, and when XX is any value except 01 and11, it indicates that the communication between terminal device and thepower supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710is further configured to receive a fifth instruction from the terminaldevice, and the fifth instruction indicates a maximum voltage of thebattery. The communication control circuit 710 is further configured totransmit a reply instruction of the fifth instruction to the terminaldevice, and the reply instruction of the fifth instruction indicatesthat the power supply device 700 has received the fifth instruction.

In an alternative implementation, a format of the fifth instruction is101100YYYYYY, and Y indicates 1 bit. The maximum voltage of the batteryis 4100+YYYYYY*10 mV.

In an alternative implementation, a format of the reply instruction ofthe fifth instruction is 101XX, X indicates 1 bit, XX=01 indicates thatthe power supply device 700 has received the fifth instruction, and whenXX is any value except 01, it indicates that the communication betweenthe terminal device and the power supply device 700 becomes abnormal.

In an alternative implementation, the communication control circuit 710is further configured to execute at least one of following operationswhen the communication between the power supply device 700 and theterminal device becomes abnormal, and the following operations include:exiting the quick charging mode, charging the battery in the normalcharging mode, stopping charging, or reactivating the quick chargingcommunication process.

In an alternative implementation, an instruction transmitted from theterminal device to the power supply device 700 contains multiple bits.When the power supply device 700 receives any instruction, the powersupply device 700 first receives a MSB of the multiple bits of the anyinstruction. Or, an instruction transmitted from the power supply device700 to the terminal device contains multiple bits. When the power supplydevice 700 transmits a certain instruction, the power supply device 700first transmits a MSB of the multiple bits of the certain instruction.

In an alternative implementation, clock signals used in thecommunication between the power supply device 700 and the terminaldevice are provided by the power supply device 700.

In an alternative implementation, an instruction transmitted from thepower supply device 700 to the terminal device contains multiple bits.During a process of transmitting each of the multiple bits, the powersupply device 700 first transmits each bit, and then transmits a clockinterrupt signal. Or, a reply instruction received from the terminaldevice by the power supply device 700 contains multiple bits. During aprocess of receiving each of the multiple bits, the power supply device700 first transmits the clock interrupt signal, and then receives eachbit after a preset time interval.

In an alternative implementation, each instruction received from theterminal device by the power supply device 700 contains a 12-bit data.The power supply device 700 receives the 12-bit data from the terminaldevice 600 via twelve continuous clock periods of the clock signal.Level of previous 500 μs of each of the twelve continuous clock periodsis high, and level of latter 10 μs of each of the twelve continuousclock periods is low. Or, each reply instruction transmitted from thepower supply device 700 to the terminal device includes a 5-bit data.The power supply device 700 transmits the 5-bit data to the terminaldevice via five continuous clock periods of the clock signal. Level ofprevious 10 μs of each of the five continuous clock periods is low, andlevel of latter 500 μs of each of the five continuous clock periods ishigh.

In an alternative implementation, during a process that the power supplydevice 700 receives an instruction from the terminal device, a minimumvalue of high level of the clock signal used between the power supplydevice 700 and the terminal device equals to VDD of the power supplydevice minus 0.7V. Or, during the process that the power supply device700 receives an instruction from the terminal device, a maximum value oflow level of the clock signal used between the power supply device 700and the terminal device is 0.8V. Or, during a process that the powersupply device 700 transmits an instruction to the terminal device, aminimum value of high level of the clock signal used between the powersupply device 700 and the terminal device equals to 0.25VDD+0.8V. Or,during the process that the power supply device 700 transmits aninstruction to the terminal device, a maximum value of the high level ofthe clock signal used between the power supply device 700 and theterminal device is 4.5V. Or, during the process that the power supplydevice 700 transmits an instruction to the terminal device, a maximumvalue of low level of the clock signal is 0.15VDD. The VDD is a workvoltage of the power supply device, and/or the VDD is greater than 3.2Vand less than 4.5V.

Those skilled in the art should appreciate that units and programmingsteps of various examples described in the implementations of thepresent disclosure can be realized by electronic hardware or acombination of computer software and electronic hardware. Whether thesefunctions are realized by hardware or software depends on particularapplications and design constraint conditions. For each particularapplication, professionals can employ different methods to realizedescribed functions, but this realization should fall into the scope ofthe present disclosure.

For convenience and simplicity, those skilled in the art can clearlyunderstand that when the specific work processes of the above describedsystems, devices, and units are described, the corresponding processesof the above method implementations can be referred, which will not berepeated herein.

In several implementations provided by the present disclosure, it can beunderstood that the disclosed systems, devices, and methods can beimplemented by other manners. For example, the device implementationsdescribed above are only schematic. For example, the units are dividedaccording to logic functions and can be divided by another manner in anactual implementation. For example, several units or assemblies can becombined or can be integrated into another system, or some features canbe ignored, or are not executed. Another point is that mutual couplingor direct coupling or communication connection shown or discussed hereincan be indirect coupling or communication connection through certaininterfaces, devices, or units, and can be in the form of electricity,machine, or other.

The units illustrated as separate units can be or cannot be physicallyseparated, and components shown in units can be or cannot be physicalunits, that is, can be in a place, or can be distributed in severalnetwork units. A part of the units or all the units can be selectedaccording to actual need to realize the purpose of the solution of theimplementations.

Additionally, various functional units in the implementations of thepresent disclosure can be integrated into one processing unit, orvarious functional units can exist alone, or two or more units can beintegrated into one unit.

If the functions can be realized in the form of software functionalunits and can be sold or used as stand-alone products, they can bestored in a computer-readable storage medium. Based on suchunderstanding, the technical solution of the present disclosure or thepart that contributes to the existing technology or a part of thetechnical solution can be embodied in the form of a software product.The computer software product can be stored in a storage medium, andinclude a plurality of instructions configured to direct a computerdevice (personal computer, server, or network device) to execute all ofor a part of steps of various implementations of the present disclosure.The storage mediums described above include a U disk, a mobile disk, aread-only memory (ROM), a random access memory (RAM), a disc, a compactdisc, or other medium storing program codes.

The foregoing descriptions are merely preferred implementations of thepresent disclosure, rather than limiting the present disclosure. Any oneskilled in the art can easily make change or alterations within thetechnology range of the present disclosure, and those change oralterations shall fall within the protection scope of the presentdisclosure. Therefore, the protection scope of the present disclosureshall be limited by the protection scope of the claims.

What is claimed is:
 1. A method of charging, comprising: determining tocharge a battery of a terminal device in a charging mode based on that acurrent status of a terminal device satisfies a condition that thebattery of the terminal device is operable to be charged in the chargingmode by a power supply device; communicating with the power supplydevice to determine a charging voltage or a charging current of thecharging mode; and communicating with the power supply device totransmit information of a current voltage of the battery to the powersupply device after the power supply device adjusts an output voltage oroutput current of the power supply device according to the chargingvoltage or the charging current of the charging mode and enters aconstant current phase to cause the power supply device to adjust theoutput current according to the current voltage of the battery.
 2. Themethod of claim 1, further comprising: communicating with the powersupply device to inform the power supply device of an impedance of acharging path of the terminal device, wherein the power supply devicedetermines whether coupling with the terminal device is bad according tothe impedance of the charging path of the terminal device, and exits thecharging mode based on a determination that the coupling with theterminal device is bad.
 3. The method of claim 1, wherein in theconstant current phase, multiple constant current charging stagescorresponding to different charging currents are conducted successively.4. The method of claim 1, further comprising: determining to charge thebattery of the terminal device in another charging mode based on thatthe current status of the terminal device satisfies a condition that thebattery of the terminal device is operable to be charged in the anothercharging mode, a charging speed of the another charging mode is slowerthan that of the charging mode.
 5. The method of claim 1, wherein thecommunication with the power supply device is conducted via instructiontransmission and instruction reception, and wherein: an instructiontransmitted comprises multiple bits, during a process of transmittingeach of the multiple bits, one bit is first transmitted via a negative(D−) data line, and then a clock interrupt signal is transmitted via apositive (D+) data line; or a reply instruction received comprisesmultiple bits, during a process of receiving each of the multiple bits,the clock interrupt signal is first received via the D+ data line, andthen one bit is received via the D− data line.
 6. A method of charging,comprises: determining to charge a battery of a terminal device in acharging mode based on that current status of the terminal devicesatisfies a condition that the battery of the terminal device isoperable to be charged in the charging mode; communicating with theterminal device to determine a charging voltage or a charging current ofthe charging mode; adjusting an output voltage or output current outputto the terminal device according to the charging voltage or the chargingcurrent of the charging mode to enter a constant current phase;communicating with the terminal device during the constant current phaseto receive information of a current voltage of the battery; andadjusting the output current output to the terminal device according tothe current voltage of the battery in the constant current phase.
 7. Themethod of claim 6, further comprising: receiving an impedance of acharging path of the terminal device; determining whether coupling withthe terminal device is bad according to the impedance of the chargingpath of the terminal device; and exiting the charging mode based on adetermination that the coupling with the terminal device is bad.
 8. Themethod of claim 6, wherein in the constant current phase, multipleconstant current charging stages corresponding to different chargingcurrents are conducted successively.
 9. The method of claim 6, furthercomprising: executing, when the communication with the terminal devicebecomes abnormal, at least one of following operations: exiting thecharging mode, charging the battery in another charging mode a chargingspeed of which is slower than that of the charging mode, and stoppingcharging the battery in the charging mode.
 10. The method of claim 6,wherein adjusting the output current output to the terminal deviceaccording to the current voltage of the battery in the constant currentphase comprises: adjusting the output current output to the terminaldevice according to a mapping relationship between voltages of thebattery and charging voltages of the charging mode.
 11. The method ofclaim 6, further comprising: determining to charge the battery of theterminal device in another charging mode based on that the currentstatus of the terminal device satisfies a condition that the battery ofthe terminal device is operable to be charged in the another chargingmode, a charging speed of the another charging mode is slower than thatof the charging mode.
 12. The method of claim 6, wherein thecommunication with the power supply device is conducted via instructiontransmission and instruction reception; an instruction transmittedcomprises multiple bits, during a process of transmitting each of themultiple bits, one bit is first transmitted via a negative (D−) dataline, and then a clock interrupt signal is transmitted via a positive(D+) data line; or a reply instruction received comprises multiple bits,during a process of receiving each of the multiple bits, the clockinterrupt signal is first received via the D+ data line, and then onebit is received via the D− data line.
 13. A power supply devicecomprising: at least one processor; and a computer readable memory,coupled to the at least one processor and storing at least one computerexecutable instruction therein which, when executed by the at least oneprocessor, causes the at least one processor to: determine to charge abattery of a terminal device in a charging mode based on that currentstatus of the terminal device satisfies a condition that the battery ofthe terminal device is operable to be charged in the charging mode;communicate with the terminal device to determine a charging voltage ora charging current of the charging mode; adjust an output voltage oroutput current output to the terminal device according to the chargingvoltage or the charging current of the charging mode to enter a constantcurrent phase; communicate with the terminal device during the constantcurrent phase to receive information of a current voltage of thebattery; and adjust the output current output to the terminal deviceaccording to the current voltage of the battery in the constant currentphase.
 14. The power supply device of claim 13, wherein the at least oneprocessor is further caused to: receiving an impedance of a chargingpath of the terminal device; determining whether coupling with theterminal device is bad according to the impedance of the charging pathof the terminal device; and exiting the charging mode based on adetermination that the coupling with the terminal device is bad.
 15. Thepower supply device of claim 13, wherein in the constant current phase,multiple constant current charging stages corresponding to differentcharging currents are conducted successively.
 16. The power supplydevice of claim 13, the at least one processor is further caused to:execute, when the communication with the terminal device becomesabnormal, at least one of following operations: exiting the chargingmode, charging the battery in another charging mode a charging speed ofwhich is slower than that of the charging mode, and stopping chargingthe battery in the charging mode.
 17. The power supply device of claim13, wherein the at least one processor caused to adjust the outputcurrent output to the terminal device according to the current voltageof the battery in the constant current phase is further caused to:adjust the output current output to the terminal device according to amapping relationship between voltages of the battery and chargingvoltages of the charging mode.
 18. The power supply device of claim 13,wherein the at least one processor is further caused to: determine tocharge the battery of the terminal device in another charging mode basedon that the current status of the terminal device satisfies a conditionthat the battery of the terminal device is operable to be charged in theanother charging mode, a charging speed of the another charging mode isslower than that of the charging mode.
 19. The power supply device ofclaim 13, wherein the communication with the power supply device isconducted via instruction transmission and instruction reception, andwherein: an instruction transmitted comprises multiple bits, during aprocess of transmitting each of the multiple bits, one bit is firsttransmitted via a negative (D−) data line, and then a clock interruptsignal is transmitted via a positive (D+) data line; or a replyinstruction received comprises multiple bits, during a process ofreceiving each of the multiple bits, the clock interrupt signal is firstreceived via the D+ data line, and then one bit is received via the D−data line.
 20. The power supply device of claim 19, wherein aninstruction received by the power supply device comprises a 12-bit data,the 12-bit data is received via twelve continuous clock periods of theclock interrupt signal, a level of previous 500 μs of each of the twelvecontinuous clock periods is high, and a level of latter 10 μs of each ofthe twelve continuous clock periods is low; or a reply instructiontransmitted by the power supply device comprises a 5-bit data, the 5-bitdata is transmitted via five continuous clock periods of the clockinterrupt signal, the level of previous 10 μs of each of the fivecontinuous clock periods is low, and the level of latter 500 μs of eachof the five continuous clock periods is high.